Asynchronous circuits do not use a clock signal for their operation. Since the clock is not present, it cannot be used to filter “glitches” or data hazards. Therefore asynchronous circuits and in particular asynchronous control circuits do not function correctly if they have any switching hazards on their signals. A transient fault can be thought of as a temporary change in a signal value—a change that causes a “glitch” in the circuit. This error can propagate and create functionality issues, including deadlocks and/or incorrect data computation.
Radiation effects complicate matters, because the impact of ionizing radiation can disrupt circuit operation at more than one electrical node simultaneously. This is because the radius of impact of the particle might be significantly larger than the smallest features in a modern electronic circuit. Therefore, a “single event” can cause multiple signals that are physically proximate to change simultaneously. Various previous authors have experimentally established this phenomenon, the most direct observation being made in memories where a single particle strike can change the state of multiple adjacent memory bits.
The field of radiation hardened electronics is a widely published and patented field. Solutions to these problems fall into two solutions domains—Solutions that address total ionization dosage (TID) of radiation, and solutions that address single event effects SEEs. The present invention affects the latter because in the field of modern CMOS VLSI fabrication, TID solutions are achieved through customized processing of the underlying silicon materials.
There is significant prior art in the space of SEE fault tolerant electronics, but, to the best knowledge of the inventors, all of the prior art is designed for use with synchronous circuits and is not applicable to the field of asynchronous circuits, which are not restricted by the presence of a clock.
There is, to the best knowledge of the inventors, little prior art in the area of asynchronous fault tolerant circuits for SEE tolerance and single event upset (SEU) immunity. The only paper known to the present inventors to be relevant to the subject describes an alternative and less effective method for the implementation of SEE tolerant quasi delay insensitive circuits in the presence of high radiation environments. See California Institute of Technology, SEU-tolerant QDI Circuits, by Jang, W. and Martin, A. J.
There thus exists a need in the art for addressing SEE and SEU faults in asynchronous circuits.